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Overview

SmartDV’s BiSS C Verification IP is a comprehensive solution for verifying the Bidirectional Serial Synchronous interface, an open-standard real-time serial protocol widely used for fast, isochronous sensor and actuator data transmission in industrial motion control and automation applications. Fully compliant with the BiSS C Protocol Description, it supports complete verification of BiSS C Master and Device components across point-to-point and bus configurations, covering standardized data formats, rotary encoder profiles, broadcast and addressed command frames, and configurable MA clock frequencies from 80 kHz.

SmartDV’s BiSS C VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With configurable baud rate control, fully configurable serial interface, configurable receive FIFO depth, constraints randomization, built-in functional coverage, and a complete test suite, SmartDV’s BiSS C VIP enables verification teams to thoroughly validate sensor and actuator interface designs for industrial automation, robotics, servo drives, and high-performance motion control applications.

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BiSS VIP
Key Features
  • Full Master and Device Support – Provides complete BiSS C Master and Device functionality with support for point-to-point and bus configurations, configurable MA clock frequency from 80 kHz, configurable baud rate control, fully configurable serial interface, and callbacks in Master, Device, and Monitor for user-defined data processing.
  • Comprehensive Frame and Data Format Support – Supports standardized BiSS C data formats, BiSS standard rotary encoder profiles, broadcast and addressed command frames, and transmit and receive commands for complete BiSS C data exchange verification.
  • Flexible Interface Configuration – Supports configurable receive FIFO depth, fully configurable serial interface parameters, and a rich set of configuration options for fine-grain BiSS C protocol control across all supported topologies.
  • Complete Verification Infrastructure – Provides built-in functional coverage analysis, constraints randomization, status counters for interface events, and callbacks in Master, Device, and Monitor for user-defined event handling and protocol violation notification.
Compliance and Compatibility
  • Fully compliant with BiSS C Protocol Description (BiSS Association e.V.)
  • Supports BiSS standard rotary encoder profile
  • Supports point-to-point and bus topologies
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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