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Overview

SmartDV’s ARINC 818 Verification IP is a comprehensive solution for verifying the Avionics Digital Video Bus, a high-bandwidth, low-latency, uncompressed digital video transmission standard designed for safety-critical avionics applications. Fully compliant with ARINC 818-3 and backward compatible with ARINC 818-2 and ARINC 818-1, it supports complete verification of ARINC 818 source and sink devices across all defined bit rates from 1.0625 Gbps to 28.05 Gbps, both 8B/10B and 64B/66B encoding, all pixel formats, aspect ratios, pixel array orders, and packing formats, with multilink support for up to three simultaneous links.

SmartDV’s ARINC 818 VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With comprehensive video, audio, and ancillary data transmission support, 32-bit full image CRC, extensive error injection and detection, interlaced and non-interlaced scan type support, built-in functional coverage, and a complete test suite, SmartDV’s ARINC 818 VIP enables verification teams to thoroughly validate avionics video bus designs for cockpit displays, sensor fusion, infrared cameras, head-up displays, helmet-mounted displays, and other high-performance aerospace and defense video applications.

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ARINC 818 VIP
Benefits
  • Full Source and Sink Device Support – Supports complete ARINC 818 source and sink device functionality with multilink operation across up to three simultaneous links, serial and parallel bit ordering, programmable FIFO depth, and a rich set of configuration parameters for fine-grain protocol control.
  • Comprehensive Bit Rate Coverage – Supports all 14 defined ARINC 818 bit rates from 1.0625 Gbps through 28.05 Gbps, including 1.0625, 1.5, 1.62, 2.125, 2.5, 3.1875, 4.25, 5.0, 6.375, 8.5, 12.75, 14.025, 21.0375, and 28.05 Gbps, with both 8B/10B and 64B/66B encoding.
  • Complete Pixel Format Support – Covers all ARINC 818 pixel formats including Monochrome, RGB, RGGB, RGBA, YIQ, YCbCr 4:2:2, Packed RGB, Packed RGGB, Packed RGBA, Packed YIQ, Packed YCbCr 4:2:2, and all Color Palette variants including Auxiliary Object, External, and Internal table formats.
  • Flexible Pixel Array and Packing Format Support – Supports all eight pixel array orders covering left-to-right, right-to-left, top-to-bottom, and bottom-to-top scan combinations, all five aspect ratios including 1:1, NTSC, and PAL, and all seven component packing formats from 8-bit through 32-bit components.
  • Video, Audio, and Ancillary Data Transmission – Supports video, audio, and ancillary data transmission as per the ARINC 818 standard, interlaced and non-interlaced scan types, 32-bit full image CRC for data integrity verification, and synchronization and segmentation across all timing classes.
  • Comprehensive Error Injection and Detection – Detects and reports invalid frame fields, invalid EOF and SOF, oversize and undersize frames, disparity errors, invalid code group errors, invalid control and data characters, sync errors, invalid packing, and CRC errors for thorough physical and protocol layer verification.
  • Complete Verification Infrastructure – Provides built-in functional coverage analysis, constraints randomization, status counters for bus events, and callbacks in source, sink, and monitor for user-defined event handling and protocol and timing violation notification.
Compliance and Compatibility
  • Fully compliant with ARINC 818-3; backward compatible with ARINC 818-2 and ARINC 818-1
  • Supports 8B/10B and 64B/66B encoding across all defined bit rates
  • Supports multilink operation up to three simultaneous links
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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