Collaboration Enables Faster, Higher-Quality Early Architecture Exploration and Pre-RTL Optimization
San Jose, CA / Santa Clara, CA – February 5, 2026 – SmartDV and Mirabilis Design today announced a strategic collaboration to deliver system-level models of SmartDV IP, enabling SoC architects and system designers to perform accurate, high-quality architecture exploration and specification optimizations well before RTL development begins.
This collaboration combines SmartDV’s production-proven IP with Mirabilis Design’s VisualSim® system-level modeling platform to provide customers with fully validated architectural models that reflect real implementation behavior. Together, the companies are addressing a critical industry need: enabling earlier, faster, and more reliable architectural decisions for increasingly complex SoCs and multi-chip systems.
Enabling Faster and More Accurate Early Architecture Exploration
Through this collaboration, SmartDV IP is available as system-level models validated against SmartDV’s RTL for power and performance.
Unlike traditional RTL-only evaluation, system-level modeling enables rapid experimentation with IP configuration parameters, SoC topology, traffic patterns, and resource allocation, delivering orders-of-magnitude faster insight into architectural choices.
“This collaboration allows our customers to move architectural validation to the very beginning of the design process,” said Deepak Kumar Tala, Managing Director, SmartDV. “Designers can now evaluate real system-level behavior using models that are validated against our production RTL, enabling better decisions and higher-quality designs.”
“System complexity continues to increase, and architectural decisions must be validated earlier than ever,” said Deepak Shankar, Founder, Mirabilis Design. “By collaborating with SmartDV, we are enabling customers to explore, optimize, and validate IP-based architectures with accuracy and confidence—well before implementation begins.”
Optimizing SmartDV IP Configuration Prior to RTL Development
A key advantage of this collaboration is the ability for customers to optimize the configuration of SmartDV IP at the architectural level, long before RTL integration begins. Architects can evaluate how different configuration choices impact system performance, power efficiency, and scalability, and then lock down validated specifications before committing to implementation.
This early optimization improves predictability, reduces downstream risk, and ensures that SmartDV IP is deployed in a way that best matches the target application and system constraints.
First Release: SmartDV CXL System-Level Model
The first product released under this collaboration is the system-level model of SmartDV’s CXL IP.
Using this model, architects can integrate SmartDV CXL into full SoC or multi-chip architectures and evaluate:
- CXL topology and host–device connectivity
- Bandwidth utilization and latency behavior
- Memory expansion and coherency traffic
- Interactions with CPUs, GPUs, NPUs, accelerators, and memory subsystems
The CXL model enables architectural experimentation such as tuning buffering strategies, arbitration policies, address mapping, and traffic distribution to significantly improve overall system efficiency. Find out more at www.mirabilisdesign.com/component/smartdv.
Looking Ahead
Both SmartDV and Mirabilis Design are committed to delivering a scalable and future-ready solution for early architecture exploration. While the initial release focuses on CXL, additional SmartDV IP blocks will be added over time, expanding coverage across protocols and applications.
The SmartDV system-level IP models are available immediately as part of the VisualSim® platform and can be integrated into customer-specific SoC architectures and workflows.
About SmartDV
At SmartDV, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force one-size-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Learn more about SmartDV at
www.smartdvtech.com
and connect with us on
LinkedIn.
About Mirabilis Design
Mirabilis Design is a Silicon Valley EDA software company for the architecture exploration of semiconductors, electronics, network and software. This solution enables the risk validation, specification optimization and requirements-tied trade-offs using a multi-domain experimentation and a large library of system modeling components. VisualSim® is the system-level modeling and simulation platform used by semiconductor, automotive, aerospace, and AI infrastructure companies to explore, validate, and optimize architectures across power, performance, and functionality. Using the OEM relationship with Cadence and the Semiconductor Vendor program, Mirabilis Design has built a portfolio of over 500 components processors, memories, interconnects, interfaces, DMA, network protocols, software task graph, RF Tx/Rx, Antennas, Power Amplifiers and cables.
Learn more about Mirabilis Design at
www.mirabilisdesign.com
and connect with us on
LinkedIn.
###
SmartDV, SmartDV Technologies, SmartDV IP Solutions, SmartDV NA, SmartCompiler, IP Your Way, and the SmartDV logo are trademarks of SmartDV Technologies India Private Limited. Any and all other trademarks present in this release are the property of their respective owners. All rights reserved.