SmartDV’s UCIe Verification IP is designed to verify die-to-die interconnects that enable scalable, high-bandwidth communication between chiplets in advanced multi-die packages. Fully compliant with the UCIe 1.0, 1.1, and 2.0 specifications, this VIP supports both short-reach (SR) and long-reach (LR) modes, along with die-to-die protocol stack validation—including physical, protocol, and software layers.

The VIP supports major verification languages, including SystemVerilog and Verilog, and integrates seamlessly with UVM, OVM, and VMM methodologies. It is simulator-independent and compatible with all leading EDA vendors’ simulators, offering broad flexibility across simulation environments.

With configurable local and remote die agents, built-in protocol checkers, error injection, lane training support, flow control validation, and coverage for all major protocol enhancements across versions 1.0 through 2.0, SmartDV’s UCIe VIP empowers verification teams to confidently validate chiplet-based architectures across AI, HPC, automotive, and data center SoCs.