SmartDV’s TileLink Verification IP is designed to verify scalable, cache-coherent on-chip interconnects commonly used in RISC-V–based SoCs. Fully compliant with the TileLink specification developed by SiFive and the RISC-V community, this VIP enables accurate validation of TileLink’s memory consistency models, transaction types, multichannel communication, and optional coherency features.

The VIP supports major verification languages, including SystemVerilog and Verilog, and integrates seamlessly with UVM, OVM, and VMM methodologies. It is simulator-independent and compatible with all leading EDA vendors’ simulators, providing flexible deployment across simulation environments.

With configurable master and slave agents, support for both TileLink Uncached (TL-UL) and TileLink Coherent (TL-C) protocols, built-in protocol checkers, error injection, and timing validation, SmartDV’s TileLink VIP empowers verification teams to confidently validate RISC-V system interconnects in both high-performance and resource-constrained designs.