SmartDV’s SVID Verification IP is a comprehensive solution for verifying the Serial VID Interface, the Intel-developed serial protocol enabling processors to dynamically request voltage levels and gather telemetry from voltage regulator modules in desktop, laptop, and server platforms. Fully compliant with SVID Specification Revision 1.7, it supports complete verification of SVID Master and Slave components across up to 15 slaves, individual slave addressing and All-Call commands to multiple slaves simultaneously, the 36-clock data frame command structure, programmable clock frequency of operation, and all defined acknowledgement types.
SmartDV’s SVID VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With comprehensive communication error handling, error detection and recovery, glitch insertion and detection, built-in functional coverage, and a complete test suite, SmartDV’s SVID VIP enables verification teams to thoroughly validate SVID interface designs for CPU power management subsystems, voltage regulator modules, motherboard VRM controllers, and any platform requiring precise dynamic voltage control between a processor and its power delivery subsystem.
