SmartDV’s RoCE Verification IP is designed to verify high-throughput, low-latency RDMA communication over Ethernet networks, widely used in data center, HPC, and storage applications. Fully compliant with both RoCE v1 and RoCE v2 specifications, this VIP enables accurate validation of RDMA transport over Layer 2 and Layer 3 Ethernet, including connection management, packet encapsulation, flow control, and error handling.

The VIP supports major verification languages, including SystemVerilog and Verilog, and integrates seamlessly with UVM, OVM, and VMM methodologies. It is simulator-independent and compatible with all leading EDA vendors’ simulators, ensuring broad applicability across simulation environments.

With configurable requester and responder agents, integrated protocol checkers, support for UDP/IP encapsulation (RoCEv2), and robust traffic generation capabilities, SmartDV’s RoCE VIP helps verification teams confidently validate high-performance, RDMA-enabled Ethernet interfaces for cloud computing, AI, and enterprise storage systems.