SmartDV’s PCI Verification IP is designed to verify legacy high-speed parallel bus interfaces used for connecting peripheral devices to processors in embedded, networking, and industrial systems. Fully compliant with the PCI Local Bus specification, this VIP enables thorough validation of address/data multiplexing, bus arbitration, configuration cycles, and interrupt handling.

The VIP supports major verification languages, including SystemVerilog and Verilog, and integrates seamlessly with UVM, OVM, and VMM methodologies. It is simulator-independent and compatible with all leading EDA vendors’ simulators, allowing flexible deployment across simulation environments.

With configurable initiator and target agents, protocol checkers, and support for 32-bit and 64-bit PCI bus widths, SmartDV’s PCI VIP empowers verification teams to confidently validate PCI-based designs, especially in legacy support scenarios or mixed-interface SoC environments.