SmartDV’s mPCIe Verification IP is designed to verify low-power, high-speed serial connectivity in mobile and embedded systems using the Mobile PCI Express architecture. Fully compliant with the mPCIe specification, this VIP enables accurate verification of layered protocol communication, including transaction, data link, and physical layers over MIPI M-PHY.

The VIP supports major verification languages, including SystemVerilog and Verilog, and integrates seamlessly with verification methodologies such as UVM, OVM, and VMM. It is simulator-independent and compatible with all leading EDA vendors’ simulators, ensuring flexible deployment across simulation environments.

Featuring configurable Root Complex and Endpoint agents, support for lane negotiation, link power management, flow control, and protocol checkers, SmartDV’s mPCIe VIP empowers design teams to validate mobile PCIe implementations used in smartphones, tablets, and other low-power SoC platforms.