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LPC Device IP
Design IP
Overview

SmartDV’s LPC (Low Pin Count) Device IP is a silicon-proven solution designed to enable reliable, low-bandwidth communication between embedded controllers and peripheral devices. Ideal for applications in legacy systems, firmware interfaces, and platform management subsystems, it offers a streamlined interface with minimal pin usage, reducing board complexity and cost.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. It ensures full compliance with the LPC specification and supports features like DMA access, I/O cycles, memory-mapped transfers, and interrupt handling for seamless system integration.

LPC Device
Benefits
Supports all transfer sizes and operations
128 bytes for firmware read
Choice of host interface: AHB, AXI, VCI, OCP, Avalon, PLB, TileLink, Wishbone, custom protocol
Compliance and Compatibility
LPC Specification v1.1
All major EDA synthesis, simulation, linting flows