SmartDV’s GDDR7 Verification IP is a comprehensive solution for verifying Graphics Double Data Rate 7 memory interfaces, the first JEDEC graphics DRAM standard to adopt PAM3 signaling for high-frequency, high-bandwidth operation. Fully compliant with JEDEC JESD239E and backward compatible with JESD239D and JESD239.01, it supports complete verification of GDDR7 device components across x8 device configurations with four independent channels and densities from 16 Gb to 128 Gb, covering all defined commands, PAM3 high-speed and NRZ low-speed data signaling, four-channel and two-channel mode operation, comprehensive RAS features including on-die ECC, data poison, CA parity with command blocking, and all defined training modes, refresh management, and power management features.
SmartDV’s GDDR7 VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With comprehensive PAM3 signaling verification, LFSR-based training with eye masking and error counters, Adaptive and Directed Refresh Management, post package repair, Dynamic Voltage Sequence support, bus-accurate timing for all timing delay ranges, built-in functional coverage, and a complete test suite, SmartDV’s GDDR7 VIP enables verification teams to thoroughly validate next-generation graphics memory interface designs for discrete GPUs, AI training and inference accelerators, cloud gaming, high-performance computing, and networking SoC applications.
