Ethernet 2.5G TSN MAC IP – SmartDV

Ethernet 2.5G TSN MAC IP

Design IP

Overview

SmartDV’s Ethernet 2.5G TSN (Time-Sensitive Networking) MAC IP Core delivers deterministic, low-latency communication for time-critical applications such as industrial control systems, automotive Ethernet, and smart factory infrastructure. It brings together the benefits of TSN and 2.5G Ethernet speed to meet the requirements of next-generation time-aware networks.

The IP core implements key IEEE 802.1 TSN features including time-aware shaper (IEEE 802.1Qbv), frame preemption (IEEE 802.1Qbu/802.3br), and precise time synchronization (IEEE 802.1AS). It also supports VLAN-based prioritization, traffic policing, and scheduled traffic delivery to ensure high reliability and predictability.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. Its modular architecture allows seamless integration with PHY interfaces such as GMII and XGMII, making it suitable for a wide range of time-sensitive Ethernet applications.

Benefits

Deterministic Multi-Gigabit Ethernet – Compliant with IEEE 802.3-2022 and Time-Sensitive Networking (TSN) standards, enabling precise and low-latency communication for 2.5G Ethernet applications
Integrated TSN Capabilities – Supports IEEE 802.1Qav Credit-Based Shaper (CBS), 802.1Qbv Time-Aware Shaper (TAS), 802.1AS for time synchronization, and 802.1Qci for stream filtering and policing
Multi-Speed Operation – Configurable to operate at 10 M/100 M/1 G/2.5 G speeds for backward compatibility and deployment in mixed-rate TSN networks
Flexible Interface Options – Provides GMII, RGMII, and XGMII interfaces for seamless connectivity to PHYs and SoCs
Precise Time Control – Supports time-stamping, gated transmissions, and per-stream scheduling to ensure bounded latency and deterministic delivery
Comprehensive Frame Management – Handles jumbo frames, control frames, pause frames, CRC/FCS insertion and checking, and VLAN tagging (IEEE 802.1Q/802.1ad)
Seamless PCS Integration – Designed to integrate directly with SmartDV 2.5G PCS IP, providing a fully verified TSN-compliant MAC-to-PHY solution for ASIC and FPGA implementations

Compliance and Compatibility

Fully compliant with IEEE 802.3-2022 and TSN standards, including IEEE 802.1Qbv, 802.1Qav, 802.1AS, and 802.1Qci
Supports multi-speed operation at 10 M/100 M/1 G/2.5 G
Compatible with GMII, RGMII, and XGMII interfaces
Compatible with all major EDA synthesis, simulation, and linting flows

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