SmartDV’s Avalon Verification IP is a comprehensive solution for verifying Intel’s Avalon interface family, a widely adopted interconnect standard for connecting components in Intel FPGA-based SoC designs. Fully compliant with the Intel Avalon Interface Specification version 22.3, it supports complete verification of all Avalon interface types including Avalon Memory-Mapped Master and Slave, Avalon Streaming Source and Sink, Avalon Conduit, Avalon Tristate Conduit, Avalon Interrupt Source and Sink, Avalon Clock Source and Sink, and Avalon Reset Source and Sink interfaces, with dedicated monitors for Avalon-MM and Avalon-ST.
SmartDV’s Avalon VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With fine-grain component control, comprehensive transfer type coverage across Avalon-MM and Avalon-ST interfaces, error injection, programmable wait states and timeouts, on-the-fly protocol checking, built-in functional coverage, and a complete test suite, SmartDV’s Avalon VIP enables verification teams to thoroughly validate Intel FPGA and SoC interconnect designs for embedded, networking, and high-performance computing applications.
