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AMBA ATB AIP
Formal Verification
Overview

SmartDV’s AMBA ATB Assertion IP provides extensive formal verification coverage tailored specifically for the AMBA ATB (Advanced Trace Bus) protocol. This pre-verified assertion IP helps identify protocol violations and functional issues early in the design cycle, ensuring reliable and accurate trace data transfer within your SoC designs.

Designed to be fully tool-agnostic, the IP integrates seamlessly with all leading EDA formal verification environments, offering maximum flexibility to verification teams regardless of their preferred tools. Delivered as synthesizable and configurable source code, it supports easy customization and reuse across different projects, enabling efficient verification workflows.

By leveraging the AMBA ATB Assertion IP, your verification process can be accelerated with improved detection of protocol compliance issues, leading to higher design quality and faster time-to-market — all within a vendor-neutral and scalable solution framework.

Benefits
  • Runs in every major formal and simulation environment
  • Simulation mode (stimulus from AMBA ATB AIP) and formal mode (stimulus from formal tool)
  • Rich set of parameters to configure functionality
  • Unencrypted SVA properties with relevant glue logic help to build an efficient FPV flow
Compliance and Compatibility
  • ARM AMBA 3 ATB v1.0
  • ARM AMBA 4 ATB v1.1