SmartDV’s technical team quickly addressed our challenges and delivered an optimal solution.

SmartDV’s MIPI CCI/CSI2 VIP is the most important VIP solution for our chip design and verification. We consider them a reliable partner for the future.

We are developing an ASIC with SmartDV’s SDIO Design IP. The customization of the Design IP ensured that our requirements were met. This was achieved based on SmartDV’s great knowledge and experience. SmartDV has also strongly supported our development by promptly and carefully evaluating prototype samples. Without SmartDV’s help, we would not have been able to proceed with our ASIC development, and we highly value SmartDV’s technical capabilities.

SmartDV’s strength lies in the individualized customization of VIP and the speed of their support. SmartDV has been flexible in responding to our requests for additional features and improving the readability of our development manuals. This is what differentiates SmartDV from other VIP vendors.

We view SmartDV as a valued and trusted partner of some of the most important VIP solutions we use in our chip design verification projects.

Often there are tweaks needed to use an IP block effectively. That usually translates into additional manpower at the vendor to implement the tweaks and associated delivery delays. This is not the case at SmartDV. Thanks to their proprietary compiler, the company can implement modifications in days.

OpenCAPI Consortium members like SmartDV will be able to create and add their own innovations to further advance differentiation and growth of the OpenCAPI ecosystem.

Our users will benefit from having access to SmartDV’s broad portfolio of design and verification IP and we welcome the opportunity to build a long-lasting relationship.

SmartDV is an industry leader for design and verification IP solutions offering comprehensive and up-to-date support for many standard protocols.

The OpenRF community looks forward to SmartDV’s expertise and the contribution it will make to our ongoing efforts to support a robust ecosystem of interoperable RF front-end and chipset platforms.