USB 3.x – SmartDV

USB 3.x

Simulation VIP

Overview

SmartDV’s USB 3.0/3.1/3.2 verification IP enables fast testbench development and verification signoff of USB hardware IP, including host, device, hub, and other RTL DUTs integrated in FPGAs, ASICs, and SoCs.

Benefits

Deployed for the verification of silicon-proven IP cores
Comprehensive library of constrained random sequences and test suite
Protocol checks, functional coverage, verification plan
Easy to instantiate and configure
Enables quick debug and root-cause analysis of RTL bugs
Error detection and insertion

Compliance and Compatibility

USB 3.0/3.1/3.2 Specification
SuperSpeed USB 3.0; SuperSpeedPlus USB 3.1, 3.2
Runs in all major simulation environments
UVM, SystemVerilog, OVM, Specman, and other verification languages and methodologies