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UFS 4.x Host
Design IP
Overview

SmartDV’s UFS (Universal Flash Storage) 4.x Host IP is a high-speed solution purpose-built for next-generation SoCs in mobile, automotive, and high-performance embedded systems. Fully compliant with JEDEC UFS 4.0/4.1 specifications, MIPI M-PHY v5.0, and MIPI UniPro v2.0 standards, it enables ultra-fast, low-latency communication with UFS 4.0-compatible memory devices.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. With advanced features including HS-Gear5 support, improved Write Booster, power-efficient Deep Sleep modes, and Host Performance Booster (HPB), SmartDV’s UFS 4.x Host IP ensures reliable, high-throughput data transfer across modern storage-intensive applications.

UFS Host
Benefits
  • Silicon-proven core
  • UFS command set layer (UCS), UFS transport protocol layer (UTP), UFS interconnect layer (UIC)
  • Priority LUN handling
  • Multiple user data partition with enhanced user data area options
  • Up to 256 outstanding commands
Compliance and Compatibility
  • UFS Specification JESD220E (UFS 3.1)
  • UFS Specification JESD220D (UFS 3.0)
  • UFS Specification JESD220E (UFS 2.1)
  • HCI Specification JESD223C
  • Unified Memory Extension Specification JESD220-1A (Version 1.1)
  • MIPI UniPro Specification 1.6, 1.8, and 2.0
  • MIPI M-PHY Specification 3.0 ,4.1, and 5.0
  • All major EDA synthesis, simulation, linting flows