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UFS 3.x Device
Design IP
Overview

SmartDV’s UFS (Universal Flash Storage) 3.x Device IP is a silicon-proven, high-speed solution built for next-generation storage requirements in mobile, automotive, and embedded platforms. Fully compliant with JEDEC UFS 3.0/3.1 specifications, MIPI M-PHY v4.1/v5.0, and MIPI UniPro v1.8, it enables ultra-fast, energy-efficient data transfer between host processors and UFS-based memory.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. With support for features such as HS-Gear4, deep sleep modes, write booster, and HPB (Host Performance Booster), SmartDV’s UFS 3.x Device IP ensures seamless integration and exceptional performance for demanding SoC environments.

UFS Device
Benefits
  • Silicon-proven core
  • UFS command set layer (UCS), UFS transport protocol layer (UTP), UFS interconnect layer (UIC)
  • Priority LUN handling
  • Multiple user data partition with enhanced user data area options
  • Up to 256 outstanding commands
Compliance and Compatibility
  • UFS Specification JESD220E (UFS 3.1)
  • UFS Specification JESD220D (UFS 3.0)
  • UFS Specification JESD220E (UFS 2.1)
  • HCI Specification JESD223C
  • Unified Memory Extension Specification JESD220-1A (Version 1.1)
  • MIPI UniPro Specification 1.6, 1.8, and 2.0
  • MIPI M-PHY Specification 3.0 ,4.1, and 5.0
  • All major EDA synthesis, simulation, linting flows