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MIPI UniPro 2.x Controller
Design IP
Overview

SmartDV’s MIPI UniPro 2.x Controller IP is a silicon-proven solution enabling high-speed, low-power interconnect for mobile, automotive, and IoT systems. Fully compliant with the MIPI Alliance UniPro 2.0 specification, it delivers robust data transport across multiple chip-to-chip and module-to-chip interfaces, including M-PHY and D-PHY.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. Its modular architecture supports features such as traffic classes, error handling, and flow control, making it ideal for integrating with protocols like UFS, CSI-3, and others requiring scalable, reliable communication.

MIPI UniPro Controller
Benefits
  • CPort arbitration at segment and packet level with a maximum of 32 CPorts
  • Multiple M-PHY lanes for UFS
  • Advanced PHY layer feature integration for link, encoding, initialization and so on
  • Various power mode support: MIPI UniPro power management modes
  • All data-link layer, network layer, transport layer features, and DME features
  • End-to-end flow control and error handling
  • L1.5 PHY testing
Compliance and Compatibility
  • MIPI UniPro Specification 1.6/1.8/2.0
  • MIPI M-PHY Specification 3.0/4.0/4.1/5.0
  • MIPI UFS Specification 2.1/3.0/3.1/4.0
  • All major EDA synthesis, simulation, and linting flows