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Overview

SmartDV’s eUSB verification IP enables fast testbench development and verification signoff of eUSB hardware IP, including host, device, and other RTL DUTs integrated in FPGAs, ASICs, and SoCs.

Benefits
Comprehensive library of constrained random sequences and test suite
Protocol checks, functional coverage, verification plan
Easy to instantiate and configure
Enables quick debug and root-cause analysis of RTL bugs
Compliance and Compatibility
USB 1.1/2.0 Specification
Embedded USB 2 (eUSB2) Physical Layer Supplement to the USB Revision 2.0 Specification Rev.1.1
High speed (480 Mbit/s), full speed (12 Mbit/s), and low speed (1.5 Mbit/s) operations
Runs in all major simulation environments
UVM, SystemVerilog, OVM, Specman, and other verification languages and methodologies