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Ethernet 25G TSN MAC
Design IP
Overview

SmartDV’s Ethernet 25G TSN (Time-Sensitive Networking) MAC IP Core brings together the precision of IEEE TSN standards and the speed of 25G Ethernet to address the needs of latency-sensitive and synchronized communication. It is ideal for industrial automation, automotive systems, and edge computing applications requiring deterministic behavior over Ethernet.

Compliant with IEEE 802.3by and TSN standards such as 802.1Qbv (time-aware shaping), 802.1Qbu/802.3br (frame preemption), and 802.1AS (time synchronization), the IP core supports VLAN tagging, traffic prioritization, and QoS enforcement. The MAC interfaces with PCS layers via XGMII or USXGMII and supports robust traffic management features for real-time applications.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance.

Ethernet 25G TSN MAC
Benefits
  • Supports Full Duplex mode
  • XGMII (32 bit) interface
  • Ultra low latency and compact implementation
  • MDIO Interface (Clause 22 and Clause 45)
  • Programmable Inter-Packet Gap (IPG) and preamble length
  • Supports FCS generation
Compliance and Compatibility
  • IEEE 802.3-2022 Ethernet Specification
  • IEEE 802.1Qbu for Preemption and IEEE 802.3br for Interspersing Express Traffic
  • IEEE 802.3 Clause 22 and Clause 45 MDIO
  • Traffic Scheduling with IEEE 802.1Qbv and IEEE 802.1Qav
  • IEEE 802.1Q
  • IEEE 1588-2008 Precision Time Protocol (PTP)
  • IEEE 802.1AS (GPTP)
  • Optional DMA Support
  • Compatible with all major EDA synthesis, simulation, and linting flows