SmartCompiler
Lorem ipsum dolor sit amet, consectetur adipiscing elit, sed do eiusmod tempor incididunt ut labore et dolore magna aliqua. Ut enim ad minim veniam, quis nostrud.
Featured // Topic
Here is where we can feature a topic or recent piece of information.
SmartViPDebug™ provides rapid analysis and debug via advanced industry-standard waveform and tabulated transaction views.
The tool speeds detection of protocol violations and gives the user the ability to troubleshoot without being an expert in a specific protocol.
SmartViPDebug supports multiple verification environments (simluation, emulation, SystemC) and includes high quality documentation to reduce ramp-up time.
SmartTestBench™ automates testbench file generation, eliminating the need for tedious, time-consuming manual creation.
The tool can create testbench files in SystemVerilog, UVM, OVM, and SystemC. It is included with all SmartDV VIP
licenses.
SmartViPDebug™ provides rapid analysis and debug via advanced industry-standard waveform and tabulated transaction views.
The tool speeds detection of protocol violations and gives the user the ability to troubleshoot without being an expert in a specific protocol.
SmartViPDebug supports multiple verification environments (simluation, emulation, SystemC) and includes high quality documentation to reduce ramp-up time.