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Overview

SmartDV’s xSPI verification IP enables fast testbench development and verification signoff of extended serial peripheral interfaces for non-volatile memory devices. The VIP includes a monitor that detects protocol violations, and master and slave bus functional models (BFMs).

Benefits
Deployed for the verification of silicon-proven IP cores
Comprehensive library of constrained random sequences and test suite
Protocol checks, functional coverage, verification plan
Easy to instantiate and configure
Enables quick debug and root-cause analysis of RTL bugs
Compliance and Compatibility
EDEC xSPI Specifications (JESD251, JESD251-A)
Runs in all major simulation environments
UVM, SystemVerilog, OVM, Specman, and other verification languages and methodologies