USB 1.x/2.x

Simulation VIP

Overview

SmartDV’s USB 1.0/1.1/2.0 verification IP enables fast testbench development and verification signoff of USB hardware IP, including Host, Device, Hub, and other RTL DUTs integrated in FPGAs, ASICs, and SoCs.

Benefits

Deployed for the verification of silicon-proven IP cores

Comprehensive library of constrained random sequences and test suite

Protocol checks, functional coverage, verification plan

Easy to instantiate and configure

Enables quick debug and root-cause analysis of RTL bugs

Compliance and Compatibility

USB 1.0/1.1/2.0 Specification

High speed (480 Mbit/s), full speed (12 Mbit/s), and low speed (1.5 Mbit/s) operations

Runs in all major simulation environments

UVM, SystemVerilog, OVM, Specman, and other verification languages and methodologies