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UFS 2.x Host
Design IP
Overview

SmartDV’s UFS (Universal Flash Storage) 2.x Host IP is a silicon-proven, high-performance solution designed for integrating fast, power-efficient storage interfaces into SoCs used in mobile, automotive, and embedded systems. The IP is fully compliant with JEDEC UFS 2.0/2.1/2.2 specifications, MIPI M-PHY v3.0/v4.1, and MIPI UniPro v1.6, enabling reliable and high-speed communication with UFS-compatible memory devices.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. The IP supports advanced features including HS-Gear3 operation, multiple power-saving modes, and native command queuing, making it ideal for high-bandwidth, low-latency applications where performance and energy efficiency are critical.

UFS Host
Benefits
  • Silicon-proven core
  • UFS command set layer (UCS), UFS transport protocol layer (UTP), UFS interconnect layer (UIC)
  • Priority LUN handling
  • Multiple user data partition with enhanced user data area options
  • Up to 256 outstanding commands
Compliance and Compatibility
  • UFS Specification JESD220E (UFS 3.1)
  • UFS Specification JESD220D (UFS 3.0)
  • UFS Specification JESD220E (UFS 2.1)
  • HCI Specification JESD223C
  • Unified Memory Extension Specification JESD220-1A (Version 1.1)
  • MIPI UniPro Specification 1.6, 1.8, and 2.0
  • MIPI M-PHY Specification 3.0 ,4.1, and 5.0
  • All major EDA synthesis, simulation, linting flows