Contact Us
Home // Design IP
UFS 3.x Host
Design IP
Overview

SmartDV’s UFS (Universal Flash Storage) 3.x Host IP is a silicon-proven, high-performance solution designed for integrating ultra-fast, low-power storage interfaces into advanced SoCs used in mobile, automotive, and high-end embedded systems. It is fully compliant with JEDEC UFS 3.0/3.1 specifications, MIPI M-PHY v4.1/v5.0, and MIPI UniPro v1.8 standards, ensuring reliable and high-bandwidth communication with UFS-compatible memory devices.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. With features including HS-Gear4 support, deep sleep and hibernation modes, Write Booster, and Host Performance Booster (HPB), SmartDV’s UFS 3.x Host IP enables seamless integration and outstanding throughput for next-generation storage applications.

UFS Host
Benefits
  • Silicon-proven core
  • UFS command set layer (UCS), UFS transport protocol layer (UTP), UFS interconnect layer (UIC)
  • Priority LUN handling
  • Multiple user data partition with enhanced user data area options
  • Up to 256 outstanding commands
Compliance and Compatibility
  • UFS Specification JESD220E (UFS 3.1)
  • UFS Specification JESD220D (UFS 3.0)
  • UFS Specification JESD220E (UFS 2.1)
  • HCI Specification JESD223C
  • Unified Memory Extension Specification JESD220-1A (Version 1.1)
  • MIPI UniPro Specification 1.6, 1.8, and 2.0
  • MIPI M-PHY Specification 3.0 ,4.1, and 5.0
  • All major EDA synthesis, simulation, linting flows