SmartDV’s UCIe (Universal Chiplet Interconnect Express) 2.x PCS IP enables high-speed, energy-efficient, and low-latency die-to-die connectivity for next-generation chiplet-based designs. Compliant with the latest UCIe 2.x specification, it supports scalable bandwidth and protocol agnostic transport, making it ideal for advanced packaging architectures in AI, HPC, and data center applications.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. It provides seamless interoperability with UCIe controllers and supports key features such as flow control, lane bonding, and clock compensation for robust and reliable chiplet communication.