SmartDV’s UCIe (Universal Chiplet Interconnect Express) 1.x PCS IP delivers a robust physical coding sublayer solution for high-bandwidth die-to-die connectivity in chiplet-based architectures. Built to support the UCIe 1.x specification, this IP core enables scalable, low-latency communication across heterogeneous dies, making it ideal for advanced packaging in AI, HPC, and data center applications.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. It supports key features such as lane bonding, link training, and data scrambling, ensuring reliable and efficient inter-die communication for next-generation multi-die systems.