TileLink

Simulation VIP

Overview

SmartDV’s TileLink verification IP provides a solution to verify the TileLink component of an SoC or ASIC. This VIP supports TileLink Uncached Lightweight (TL-UL), TileLink Uncached Heavyweight (TL-UH), and TileLink Cached (TL-C) conformance levels.

Benefits

Rich set of configuration parameters to control TileLink functionality
Status counters for various events on bus
Easy-to-use command interface simplifies testbench control and configuration of master and slave
Simplifies results analysis
Faster testbench development and more complete verification of TileLink designs
Includes a complete test suite to test every feature of the TileLink Specification

Compliance and Compatibility

TileLink Specification v1.8.1
All major simulation environments