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Overview

SmartDV’s QSPI verification IP enables fast testbench development and verification signoff of quad serial peripheral interfaces. The VIP includes a monitor that detects protocol violations, and master and slave bus functional models (BFMs).

Benefits
Deployed for the verification of silicon-proven IP cores
Comprehensive library of constrained random sequences and test suite
Protocol checks, functional coverage, verification plan
Easy to instantiate and configure
Enables quick debug and root-cause analysis of RTL bugs
Supports Serial Flash Discoverable Parameters (SFDP) mode and security features
Compliance and Compatibility
Macronix, Windbond, Micron QSPI devices
W25Q128FW, W25Q128FVSIQ, W25Q128JVDTR, W25Q128JVSIQ,
MT25QL128ABA, MX25L12872F, MX25L12873G, MX25l51245G, PCT26WF032, SST26VF016, SST26VF032
Runs in all major simulation environments
UVM, SystemVerilog, OVM, Specman, and other verification languages and methodologies