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Overview

SmartDV’s PCIe verification IP enables fast testbench development and verification signoff of the peripheral component interconnect express hardware. The PCIe VIP includes a monitor that detects protocol violations, and root complex and endpoint bus functional models (BFMs).

Benefits
  • Comprehensive library of constrained random sequences and test suite
  • Protocol checks, functional coverage, verification plan
  • Easy to instantiate and configure
  • Enables quick debug and root-cause analysis of RTL bugs
Compliance and Compatibility
  • PCI-SIG PCI Express 1.0/2.0/3.0/4.0/5.0/6.0 Specifications
  • Runs on all major simulators