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Octal SPI
Simulation VIP
Overview

SmartDV’s OSPI verification IP enables fast testbench development and verification signoff of octal serial peripheral interfaces. This serial synchronous communication protocol was developed by Macronix. The VIP includes a monitor that detects protocol violations, and master and slave bus functional models (BFMs).

Benefits
Deployed for the verification of silicon-proven IP cores
Comprehensive library of constrained random sequences and test suite
Protocol checks, functional coverage, verification plan
Easy to instantiate and configure
Enables quick debug and root-cause analysis of RTL bugs
Supports Serial Flash Discoverable Parameters (SFDP) mode and security features
Compliance and Compatibility
Macronix CMOS MXSMIO® (SERIAL MULTI I/O) flash memory specification
Runs in all major simulation environments
UVM, SystemVerilog, OVM, Specman, and other verification languages and methodologies