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Overview

SmartDV’s OCP verification IP provides a solution to verify the Open Core Protocol component of an SoC or ASIC. It includes an efficient, bus-independent, configurable, and highly scalable interface for on-chip subsystem communications. OCP supports multithreading, synchronization primitives, and single-request/multiple-data transactions. OCP data transfer models range from simple request-grant handshaking through pipelined request-response to complex out-of-order operations.

Benefits
  • Asynchronous/synchronous reset and EnableClk mechanism, with on-the-fly reset control
  • Ability to pipeline transfers and non-blocking flow control support
  • Status counters for various events on bus
  • Easy-to-use command interface simplifies testbench control and configuration of master and slave
  • Rich set of configuration parameters to control OCP functionality
  • Faster testbench development and more complete verification of OCP designs with simplified results analysis
Compliance and Compatibility
  • Accellera OCP 3.1 Specification
  • All major simulation environments