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MIPI SPMI Master
Design IP
Overview

SmartDV’s MIPI SPMI (System Power Management Interface) Master IP is a silicon-proven solution designed to streamline power management communication between application processors and multiple peripheral components. Compliant with the MIPI SPMI specification, it enables efficient, low-latency control of voltage regulators and other power management devices in mobile, automotive, and IoT platforms.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. Its robust architecture supports multiple slave devices, dynamic channel management, and fast wake-up sequences, making it an ideal choice for energy-sensitive system designs.

MIPI SPMI Master
Benefits
  • The following frames are supported:
    • Command
    • Data/address
    • No response
  • Glitch suppression (optional)
  • Transfer bus ownership command sequence
  • Connect/disconnect sequence
  • Host controller interface for command queue based master command processing (optional)
  • HCI contains DMA engine
  • Master priority arbitration
  • Extended register read/writes
  • Baud rate control
  • Low power modes
  • Wakeup command
  • Authentication command sequence
  • Device descriptor block command sequences
Compliance and Compatibility
  • MIPI SPMI Specification 1.0 and 2.0
  • ACK/NACK (per 2.0 Spec)