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MIPI I3C SMaster
Design IP
Overview

SmartDV’s MIPI I3C SMaster IP is a silicon-proven, dual-role solution compliant with the MIPI I3C v1.2 specification, supporting both Master and Slave functionalities in a single, integrated IP core. Ideal for complex SoC designs in mobile, automotive, and IoT applications, the SMaster IP enables seamless role-switching, multi-controller environments, and advanced communication features like in-band interrupts, hot-join, dynamic address assignment, and high data rates.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. It simplifies integration in SoCs that require hybrid controller and peripheral capabilities, reducing silicon footprint and improving connectivity efficiency. Optional support for I3C HCI (Host Controller Interface) streamlines software integration and enhances overall system flexibility.

MIPI I3C SMaster
Benefits
  • Combines master and slave functionality
  • Built-in support for JEDEC and MCTP
  • Two-wire serial interface up to 12.5 MHz
  • Offered with or without HCI (host command interface)
  • DMA mode
  • Supports all topologies; single/multi master/slave combinations
  • Advanced addressing and address arbitration
  • HDR with DDR, direct CCC and broadcast CCC
  • Legacy I2C device coexistence on the same bus instance
Compliance and Compatibility
  • MIPI I3C Specification v1.0, v1.1
  • I3C HCI Specification v1.0, v1.1
  • JEDEC Module Sideband Bus Specification v1.0
  • MCTP I3C Transport Binding Specification v3.0