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MIPI I3C Slave
Design IP
Overview

SmartDV’s MIPI I3C Slave IP is a silicon-proven solution compliant with the MIPI I3C v1.2 specification, enabling efficient and intelligent communication with I3C Master devices across sensor-rich applications in mobile, automotive, and IoT systems. It supports dynamic address assignment, in-band interrupts, hot-join, high data rates, and is backward compatible with I²C. Optional I3C HCI (Host Controller Interface) support is available for enhanced software interfacing and system-level integration.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. It enables seamless integration into SoC architectures requiring low-pin-count, power-efficient peripheral connectivity.

MIPI I3C Slave
Benefits
  • Two-wire serial interface up to 12.5 MHz
  • Supports all topologies; single/multi master/slave combinations
  • Advanced addressing and address arbitration
  • HDR with DDR, direct CCC and broadcast CCC
  • Legacy I2C device coexistence on the same bus instance
Compliance and Compatibility
  • MIPI I3C Specification v1.0, v1.1