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MIPI DSI-2 Transmitter
Design IP
Overview

SmartDV’s MIPI DSI-2 Transmitter IP is a silicon-proven solution designed to drive high-performance display interfaces across mobile, automotive, and embedded systems. Fully compliant with the MIPI DSI-2 v2.2 specification, it enables low-power, high-speed transmission of video and command data with support for Display Stream Compression (DSC), VESA formats, and both video and command modes.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. It integrates seamlessly with MIPI D-PHY and C-PHY interfaces, delivering scalable bandwidth and efficient display connectivity for next-generation SoCs.

MIPI DSI-2 Transmitter
Benefits
  • Permits multiple packets per transmission
  • Bidirectional communication and low power mode
  • Multi-lane capability
  • Supports all pixel formats; configurable
  • Multiple pixels per clock
  • Programmed to support either video mode or command mode
  • Virtual channel capability
  • Standard PPI interface towards DPHY and CPHY
  • Interrupt support for indicating internal status and error information
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • Comprehensive set of deliverables, including scripts, documentation, and testbench
Compliance and Compatibility
  • MIPI DSI-2 Bus Specification v1.3
  • Display Pixel Interface (DPI -2) v2.0
  • Display Bus Interface (DBI) v2.0
  • Display Command Set (DCS) v1.3
  • D-PHY Specification v1.1, v1.2, v2.0, v2.1
  • C-PHY Specification v0.7, v1.2