Overview
SmartDV’s JESD403 (SidebandBus) verification IP provides a simple and efficient way to verify the JESD403 bidirectional two-wire serial interface. The model has a rich set of configuration parameters to set clock synchronization and generation of the serial clock line (SCL) to meet all clocking requirements. This VIP operates as a master or slave. As a master, the model can start/stop all possible transfers. As a slave device, it can detect start/stop conditions and perform data transfers according to the initiator request.