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JESD403 (SidebandBus)
Simulation VIP
Overview

SmartDV’s JESD403 (SidebandBus) verification IP provides a simple and efficient way to verify the JESD403 bidirectional two-wire serial interface. The model has a rich set of configuration parameters to set clock synchronization and generation of the serial clock line (SCL) to meet all clocking requirements. This VIP operates as a master or slave. As a master, the model can start/stop all possible transfers. As a slave device, it can detect start/stop conditions and perform data transfers according to the initiator request.

Benefits
Two-wire serial interface up to 12.5 MHz
Dynamic address assignment, including static addressing for legacy I2C devices
Host device addess
Timed reset
Write/read formats
PEC enable/disable
Master SCL clock stalling
Slave error types S1 and S2
Compliance and Compatibility
JEDEC JESD403 Specification v.1.0
Full JESD403 host controller and device functionality