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JESD207
Simulation VIP
Overview

SmartDV’s JESD207 verification IP provides a simple and efficient way to verify the radio front end – baseband digital parallel (RBDP) interface between a radio front end integrated circuit (RFIC) and a baseband integrated circuit (BBIC), as defined in the JESD207 Protocol Specification. This VIP operates as BBIC and RFIC monitor.

Benefits
Faster testbench development and more complete verification of JESD207 designs
Easy-to-use command interface simplifies testbench control and configuration of BBIC and RFIC
Supports both datapath and control plane transactions
Multiple parallel sample streams in BBIC and RFIC datapath interface
Includes a complete test suite to verify all features of JESD207
Compliance and Compatibility
JEDEC JESD207 Protocol Specification
Runs in all major simulation environments