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Ethernet 10G TSN MAC
Design IP
Overview

SmartDV’s Ethernet 10G TSN (Time-Sensitive Networking) MAC IP Core combines the benefits of deterministic Ethernet with high-speed 10G performance, delivering precise, low-latency communication for time-critical applications such as industrial automation, automotive Ethernet, and smart grid systems.

The IP core is compliant with IEEE 802.3ae and supports TSN features including time-aware shaper (IEEE 802.1Qbv), frame preemption (IEEE 802.1Qbu/802.3br), and IEEE 802.1AS-based time synchronization. It also enables traffic prioritization, ingress policing, and VLAN tagging for fine-grained traffic control.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. With support for XGMII and integration into standard Ethernet subsystems, the 10G TSN MAC IP Core is well-suited for applications requiring real-time performance and high data integrity.

Ethernet 10G TSN MAC
Benefits
  • Supports Full Duplex mode
  • XGMII (32 bit) interface
  • Ultra low latency and compact implementation
  • MDIO Interface (Clause 22 and Clause 45)
  • Programmable Inter-Packet Gap (IPG) and preamble length
  • Supports FCS generation
Compliance and Compatibility
  • IEEE 802.3-2022 Ethernet Specification
  • IEEE 802.1Qbu for Preemption and IEEE 802.3br for Interspersing Express Traffic
  • IEEE 802.3 Clause 22 and Clause 45 MDIO
  • Traffic Scheduling with IEEE 802.1Qbv and IEEE 802.1Qav
  • IEEE 802.1Q
  • IEEE 1588-2008 Precision Time Protocol (PTP)
  • IEEE 802.1AS (GPTP)
  • Optional DMA Support
  • Compatible with all major EDA synthesis, simulation, and linting flows