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Ethernet 50G TSN MAC
Design IP
Overview

SmartDV’s Ethernet 50G TSN (Time-Sensitive Networking) MAC IP Core combines 50G Ethernet throughput with deterministic networking features to meet the needs of industrial automation, autonomous systems, and edge computing. Built on IEEE 802.3by and IEEE 802.1 TSN standards, the IP core supports critical TSN features including time-aware shaper (TAS – IEEE 802.1Qbv), frame preemption (IEEE 802.1Qbu/802.3br), and precise time synchronization (IEEE 802.1AS).

Additional capabilities such as VLAN support, traffic shaping, frame filtering, and advanced QoS mechanisms make it ideal for time-critical data flows over Ethernet.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. Compatibility with PHY interfaces like XGMII and CGMII ensures seamless integration into high-performance TSN-enabled systems.

Ethernet 100G TSN MAC
Benefits
  • Supports Full Duplex mode
  • XLGMII / CGMII (64 bit) interface
  • Ultra low latency and compact implementation
  • MDIO Interface (Clause 22 and Clause 45)
  • Programmable Inter-Packet Gap (IPG) and preamble length
  • Supports FCS generation
Compliance and Compatibility
  • IEEE 802.3-2022 Ethernet Specification
  • IEEE 802.1Qbu for Preemption and IEEE 802.3br for Interspersing Express Traffic
  • IEEE 802.3 Clause 22 and Clause 45 MDIO
  • Traffic Scheduling with IEEE 802.1Qbv and IEEE 802.1Qav
  • IEEE 802.1Q
  • IEEE 802.3.az Energy Efficient Ethernet(EEE)
  • IEEE 1588-2008 Precision Time Protocol (PTP)
  • IEEE 802.1AS (GPTP)
  • Optional DMA Support
  • Compatible with all major EDA synthesis, simulation, and linting flows