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Ethernet 100G TSN MAC
Design IP
Overview

SmartDV’s Ethernet 100G TSN (Time-Sensitive Networking) MAC IP Core is a specialized, high-performance solution that enables deterministic and low-latency data communication for mission-critical applications. Tailored for industrial automation, automotive Ethernet, and 5G transport networks, it combines IEEE 802.1 TSN features with 100G Ethernet performance to support synchronized, time-aware data transmission.

The IP core is compliant with IEEE 802.3 and incorporates key TSN capabilities such as time-aware shaper (TAS – IEEE 802.1Qbv), frame preemption (IEEE 802.1Qbu/802.3br), scheduled traffic, and precise time synchronization (IEEE 802.1AS). It also supports VLAN tagging, traffic classification, and ingress policing for enhanced traffic control and QoS enforcement.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. Integrated with standard PHY interfaces like XLGMII and CGMII, the 100G TSN MAC IP enables scalable deployment in systems that require ultra-reliable and time-sensitive communication.

Benefits
  • Supports Full Duplex mode
  • XGMII (32 bit) interface
  • Ultra low latency and compact implementation
  • MDIO Interface (Clause 22 and Clause 45)
  • Programmable Inter-Packet Gap (IPG) and preamble length
  • Supports FCS generation
Compliance and Compatibility
  • IEEE 802.3-2022 Ethernet Specification
  • IEEE 802.1Qbu for Preemption and IEEE 802.3br for Interspersing Express Traffic
  • IEEE 802.3 Clause 22 and Clause 45 MDIO
  • Traffic Scheduling with IEEE 802.1Qbv and IEEE 802.1Qav
  • IEEE 802.1Q
  • IEEE 1588-2008 Precision Time Protocol (PTP)
  • IEEE 802.1AS (GPTP)
  • Optional DMA Support
  • Compatible with all major EDA synthesis, simulation, and linting flows