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eSPI Slave to LPC Bridge
Design IP
Overview

SmartDV’s eSPI Slave to LPC Bridge IP is a silicon-proven solution that enables seamless interoperability between next-generation systems using eSPI (Enhanced Serial Peripheral Interface) and legacy devices operating on the LPC (Low Pin Count) interface. Fully compatible with Intel’s eSPI and LPC specifications, this bridge IP facilitates smooth system migration by preserving access to LPC-based peripherals in modern embedded, automotive, and industrial applications.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. It supports key eSPI command sets, including I/O, memory, and message cycles, along with power management features such as out-of-band (OOB) signaling and virtual wire communication. The bridge also handles serialization/deserialization and timing management, ensuring reliable, low-latency performance.

eSPI Slave to LPC Bridge
Benefits
  • Converts eSPI Peripheral Channel Transactions into LPC Memory write or read
    instructions
  • Supports eSPI Slave
    • Supports multiple channels: Peripheral, Virtual Wires, OOB Message, and Runtime Flash Access
    • Supports various reset types:
      • eSPI reset from Master to Slave
      • eSPI reset from Slave to Master
      • In-band reset command
  • Supports LPC Master Interface
    • Incorporates Serial IRQ Interface support
    • Allows for a variable number of wait-states
    • Supports frames for LPC operations: I/O write and read, Memory write and read
Compliance and Compatibility
  • eSPI Base Specification Rev.1.5
  • LPC specification v1.1
  • All major EDA synthesis, simulation, linting flows