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eSPI Slave
Design IP
Overview

SmartDV’s eSPI (Enhanced Serial Peripheral Interface) Slave IP is a silicon-proven solution designed to enable efficient, low-pin-count communication between embedded controllers and peripheral devices. Fully compliant with the Intel eSPI specification, it supports out-of-band signaling, lower power operation, and advanced management features for modern platform architectures.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. With robust support for legacy SPI compatibility, virtual wire channels, and peripheral and OOB channels, SmartDV’s eSPI Slave IP is ideal for PC, server, and embedded applications demanding compact, cost-effective system connectivity.

eSPI Slave
Benefits
  • Supports multiple channels: Peripheral, Virtual Wires, OOB Message, and Runtime Flash Access
  • Supports various reset types:
    • eSPI reset from Master to Slave
    • eSPI reset from Slave to Master
    • In-band reset command
  • Operates in Single, Dual, and Quad modes
  • Capable of Slave-triggered transactions
  • Features power management events
Compliance and Compatibility
  • eSPI Base Specification Rev.1.5
  • SPI Block Guide 4.01 Standard
  • All major EDA synthesis, simulation, linting flows