SmartDV’s CXL (Compute Express Link) 3.x Controller IP brings high-speed, coherent connectivity with enhanced fabric capabilities—supporting memory-centric architectures and disaggregated compute environments at scale. Fully compliant with the CXL 3.x specification, it introduces features such as multi-level switching, memory sharing across multiple hosts, and support for global fabric-attached memory.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. SmartDV’s CXL 3.x IP supports backward compatibility with CXL 1.x and 2.0, includes advanced security features, and offers robust scalability for building memory fabrics and dynamic topology-aware systems in modern data centers.