SmartDV’s CXL (Compute Express Link) 2.0 Controller IP extends support for advanced memory pooling, switching, and persistent memory, enhancing scalability and resource efficiency for high-performance computing, AI, and cloud infrastructure. Fully compliant with the CXL 2.0 specification, it enables dynamic resource sharing through support for memory and device disaggregation over a common PCIe infrastructure.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. With features like IDE (Integrity and Data Encryption), enhanced fabric management, and dynamic device enumeration, SmartDV’s CXL 2.0 Controller IP is ideal for next-gen heterogeneous systems requiring secure and flexible connectivity.