SmartDV’s CXL (Compute Express Link) 1.x Controller IP enables high-speed, low-latency, and cache-coherent communication between CPUs, memory, and accelerators—addressing the performance demands of next-generation data centers and high-performance computing (HPC) applications. Fully compliant with the CXL 1.0 and 1.1 specification, it supports CXL.io, CXL.cache, and CXL.mem protocols, ensuring seamless integration into diverse system architectures.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. With robust support for coherency management, protocol layering, and configurable lane widths, the CXL 1.x Controller IP is ideal for designs seeking scalable bandwidth and efficient memory sharing across heterogeneous compute environments.