SmartDV’s CHI to UCIe Bridge IP enables seamless protocol translation between Arm’s Coherent Hub Interface (CHI) and the Universal Chiplet Interconnect Express (UCIe) standard, facilitating high-bandwidth, low-latency communication in multi-die and chiplet-based designs. This bridge IP is ideal for next-generation SoCs requiring cache-coherent communication across die boundaries while leveraging the open UCIe ecosystem.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. Its modular architecture ensures easy integration into diverse system architectures, helping accelerate time-to-market for advanced heterogeneous computing platforms.